In fabrication of MOS devices designed to have feature sizes of 0.35 .mu.m or less, techniques for silicidation of source/drain regions and a polysilicon gate have come into wide use in MOS transistors. Of these techniques, methods for forming a self-aligned silicide region in MOS devices are disclosed in U.S. Pat. Nos. 5,567651 and 5,605,866. These silicidation methods have been employed reduce sheet resistance in an excellent ohmic contact, source/drain region, and polysilicon interconnections; to provide an increased effective contact area; and to provide an etch stopping function.
Other known methods for fabricating MOS devices having a salicide and LDD structure are disclosed in U.S. Pat. Nos. 5,089,865, 5,508,212 and 5,554,549. In these methods, alternative materials such as cobalt, platinum, palladium, nickel, molybdenum or the like are used as salicide materials. Of these salicide materials, particularly, cobalt silicide has lower resistivity in comparison to the other salicide materials, allows low temperature processing, and allows suppression of latch up at an interface of a junction region.
There is a primary known method of forming a MOS transistor having Co-silicide (cobalt silicide) and an LDD structure. In this method, a sidewall spacer formed gate structure is first formed on a semiconductor substrate, and then lightly and heavily doped impurity regions used as source/drain regions are formed by ion implantations using the gate structure as a mask. A layer of cobalt is deposited on an upper polysilicon surface of the gate structure and on an upper surface of the heavily doped impurity region using a chemical vapor deposition process.
Following the cobalt deposition, a first heat treatment, for example, a rapid thermal annealing is carried out at a low temperature in the range of 400.degree. C. to 500.degree. C. to form Co.sub.2 Si and CoSi where the cobalt layer is in intimate contact with the silicon or polysilicon regions. After forming the Co.sub.2 Si and CoSi compounds a second heat treatment is further carried out at a higher temperature to transform the Co.sub.2 Si and CoSi compounds into CoSi.sub.2. CoSi.sub.2 has a lower resistivity than Co.sub.2 Si and CoSi formed in the initial annealing process.
However, under this process of fabricating devices void defects are thereby formed in the cobalt silicide (CoSi.sub.2) layer. These voids are generated having a diameter in the range of about 800 .ANG. to 2000 .ANG.. This leads to an increase in junction leakage current of the respective devices. As a result, the conventional MOS transistor having voids in cobalt silicide have deteriorated electrical characteristics.
The following three reasons such void defects are generated in CoSi.sub.2 can be observed as evident by using a scanning electron microscope.
(1) An active region of a semiconductor substrate has become damaged during a dry etching process of a very thin (about 50 .ANG. or less) gate insulating layer (for example, a gate oxide layer).
(2) The active region of the semiconductor substrate has become damaged during a dry etching process of forming a gate sidewall spacer.
(3) The active region has become damaged by injecting impurity ions directly into exposed silicon, wherein the impurity ions are accelerated with high energy.
For the above-mentioned reasons, cobalt and silicon atoms at an interface area between the cobalt and silicon layers are locally accelerated or delayed while diffusing by the heat treatment, whereby the void defects are generated.
Herein, we should give attention to the fact that damage of the active region generated due to the above reasons (1) and (2) can be sufficiently prevented by using a higher etch selectivity with respect to the gate oxide layer. The invention is thus provided to solve a problem of void defects caused by the above reason (3), that is, to prevent the active region from becoming damaged during the ion implantation for forming a heavily doped region in the active region.